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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tlv702-q1 slvsc35c ? august 2013 ? revised january 2018 tlv702-q1 300-ma, low-i q , low-dropout regulator 1 1 features 1 ? qualified for automotive applications ? aec-q100 qualified with the following results: ? device temperature grade 1: ? 40 c to 125 c ambient operating temperature range ? device hbm esd classification level h2 ? device cdm esd classification level c4b ? very low dropout: ? 37 mv at i out = 50 ma, v out = 2.8 v ? 75 mv at i out = 100 ma, v out = 2.8 v ? 220 mv at i out = 300 ma, v out = 2.8 v ? 2% accuracy over temperature ? low i q : 35 a ? fixed-output voltage combinations possible from 1.2 v to 4.8 v ? high psrr: 68 db at 1 khz ? stable with effective capacitance of 0.1 f (1) ? thermal shutdown and overcurrent protection ? packages: 5-pin sot (dbv and ddc) and 1.5-mm 1.5-mm, 6-pin wson (1) see the input and output capacitor requirements in the application information section. 2 applications ? automotive camera modules ? image sensor power ? microprocessor rails ? automotive infotainment head units ? automotive body electronics 3 description the tlv702-q1 series of low-dropout (ldo) linear regulators are low quiescent current devices with excellent line and load transient performance. these ldos are designed for power-sensitive applications. a precision bandgap and an error amplifier provide overall 2% accuracy. low output noise, very high power-supply rejection ratio (psrr), and low-dropout voltage make this series of devices ideal for a wide selection of battery-operated equipment. all device versions have thermal shutdown and current limit protections for safety. furthermore, these devices are stable with an effective output capacitance of only 0.1 f. this feature enables the use of cost-effective capacitors that have higher bias voltages and temperature derating. the devices regulate to specified accuracy with no output load. the tlv702-q1 series of ldo linear regulators is available in sot and wson packages. device information (1) part number package body size (nom) tlv702-q1 sot (5) 2.90 mm 1.60 mm wson (6) 1.50 mm 1.50 mm (1) for all available packages, see the package option addendum at the end of the data sheet. typical application productfolder tlv702-q1 gnd en in out v in v out on off c in 1 f ceramic c out support &community tools & software technical documents ordernow
2 tlv702-q1 slvsc35c ? august 2013 ? revised january 2018 www.ti.com product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 typical characteristics .............................................. 6 7 detailed description ............................................ 10 7.1 overview ................................................................. 10 7.2 functional block diagrams ..................................... 10 7.3 feature description ................................................. 10 7.4 device functional modes ........................................ 11 8 application and implementation ........................ 12 8.1 application information ............................................ 12 8.2 typical application .................................................. 12 9 power supply recommendations ...................... 14 9.1 power dissipation ................................................... 14 10 layout ................................................................... 14 10.1 layout guidelines ................................................. 14 10.2 layout examples ................................................... 15 11 device and documentation support ................. 16 11.1 device support .................................................... 16 11.2 documentation support ........................................ 16 11.3 receiving notification of documentation updates 16 11.4 community resources .......................................... 16 11.5 trademarks ........................................................... 16 11.6 electrostatic discharge caution ............................ 16 11.7 glossary ................................................................ 17 12 mechanical, packaging, and orderable information ........................................................... 17 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision b (june 2015) to revision c page ? added dbv package to document ......................................................................................................................................... 1 ? changed packages features bullet to include dbv package ............................................................................................... 1 ? added dbv package to pin configuration and functions section ......................................................................................... 3 ? added dbv column to thermal information table .................................................................................................................. 4 ? changed title of layout example for the ddc and dbv packages figure to include dbv package ................................... 15 changes from revision a (august 2013) to revision b page ? added dse (6-pin wson) package to data sheet ................................................................................................................ 1 ? added device information , esd ratings , and recommended operating conditions tables, and detailed description , application and implementation , power supply recommendations , layout , device and documentation support , and mechanical, packaging, and orderable information sections to data sheet .................................................... 1 ? deleted all references to p version of device throughout data sheet ..................................................................................... 1 ? added " over temperature " to 2% accuracy features bullet ................................................................................................ 1 ? changed ddc package name from tsot23 to sot throughout data sheet ........................................................................ 1 ? changed applications bullets ................................................................................................................................................. 1 ? changed description section text ........................................................................................................................................... 1 ? changed ceramic capacitor units on typical application circuit from mf to f (typo) ......................................................... 1 ? changed " free-air temperature " to " junction temperature " in absolute maximum ratings condition statement .................... 4 ? added t j to t a condition in electrical characteristics condition statement ............................................................................ 5 ? changed t a to t j for typical values in electrcial characteristics condition statement ........................................................... 5
3 tlv702-q1 www.ti.com slvsc35c ? august 2013 ? revised january 2018 product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated 5 pin configuration and functions ddc and dbv package 5-pin sot top view dse package 6-pin wson top view pin functions pin i/o description name ddc, dbv (sot) dse (wson) in 1 1 i input pin. a small, 1- f ceramic capacitor is recommended from this pin to ground to assure stability and good transient performance. see input and output capacitor requirements in the application information section for more details. gnd 2 2 ? ground pin en 3 6 i enable pin. driving en over 0.9 v turns on the regulator. driving en below 0.4 v puts the regulator into shutdown mode and reduces operating current to 1 a, nominal. nc 4 4, 5 ? no connection. tie this pin to ground to improve thermal dissipation. out 5 5 o regulated output voltage pin. a small, 1- f ceramic capacitor is needed from this pin to ground for stability. see input and output capacitor requirements in the application information section for more details. enn/c n/c 6 5 4 in gnd out 1 2 3 outnc in gnd en 12 3 5 4
4 tlv702-q1 slvsc35c ? august 2013 ? revised january 2018 www.ti.com product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to network ground terminal. 6 specifications 6.1 absolute maximum ratings over operating junction temperature range (unless otherwise noted) (1) min max unit voltage (2) in ? 0.3 6 v en ? 0.3 6 v out ? 0.3 6 v current (source) out internally limited a output short-circuit duration indefinite temperature operating virtual junction, t j ? 55 150 c storage, t stg ? 55 150 c (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) 2000 v charged-device model (cdm), per aec q100-011 750 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v in 2 5.5 v v out 1.2 4.8 v i out 0 300 ma ambient temperature, t a ? 40 125 c operating virtual junction temperature, t j ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) tlv702-q1 unit ddc (sot) dbv (sot) dse (wson) 5 pins 5 pins 6 pins r ja junction-to-ambient thermal resistance 262.8 249.2 321.3 c/w r jc(top) junction-to-case (top) thermal resistance 68.2 136.4 207.9 c/w r jb junction-to-board thermal resistance 81.6 85.9 281.5 c/w jt junction-to-top characterization parameter 1.1 19.5 42.4 c/w jb junction-to-board characterization parameter 80.9 85.3 284.8 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a n/a 142.3 c/w
5 tlv702-q1 www.ti.com slvsc35c ? august 2013 ? revised january 2018 product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated (1) v do is measured for devices with v out(nom) 2.35 v. (2) start-up time = time from en assertion to 0.98 v out(nom) . 6.5 electrical characteristics at v in = v out(nom) + 0.5 v or 2 v (whichever is greater); i out = 10 ma, v en = 0.9 v, c out = 1 f, and t j , t a = ? 40 c to +125 c, unless otherwise noted. typical values are at t j = 25 c. parameter test conditions min typ max unit dc output accuracy ? 2% 0.5% 2% v o( vi) line regulation v out(nom) + 0.5 v v in 5.5 v, i out = 10 ma 1 5 mv v o( io) load regulation 0 ma i out 300 ma 1 15 mv v do dropout voltage (1) v in = 0.98 v out(nom) , i out = 300 ma 260 375 mv i cl output current limit v out = 0.9 v out(nom) 320 500 860 ma i gnd ground pin current i out = 0 ma 35 55 a i out = 300 ma, v in = v out + 0.5 v 370 a i shdn ground pin current (shutdown) v en 0.4 v, v in = 2 v 400 na v en 0.4 v, 2 v v in 4.5 v 1 2.5 a psrr power-supply rejection ratio v in = 2.3 v, v out = 1.8 v, i out = 10 ma, f = 1 khz 68 db v n output noise voltage bw = 100 hz to 100 khz, v in = 2.3 v, v out = 1.8 v, i out = 10 ma 48 v rms t str start-up time (2) c out = 1 f, i out = 300 ma 100 s v en(high) enable pin high (enabled) 0.9 v in v v en(low) enable pin low (disabled) 0 0.4 v i en enable pin current v in = v en = 5.5 v 0.04 a uvlo undervoltage lockout v in rising 1.9 v t sd thermal shutdown temperature shutdown, temperature increasing 165 c reset, temperature decreasing 145 c
6 tlv702-q1 slvsc35c ? august 2013 ? revised january 2018 www.ti.com product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated 6.6 typical characteristics over operating temperature range (t j = ? 40 c to +125 c), v in = v out(nom) + 0.5 v or 2 v, whichever is greater; i out = 10 ma, v en = v in , c out = 1 f, unless otherwise noted. typical values are at t j = 25 c. figure 1. line regulation figure 2. line regulation figure 3. load regulation figure 4. dropout voltage vs input voltage figure 5. dropout voltage vs output current figure 6. output voltage vs temperature 1.901.88 1.86 1.84 1.82 1.80 1.78 1.76 1.74 1.72 1.70 v out (v) 2.1 2.6 3.1 3.6 4.1 4.6 5.1 v (v) in 5.6 +125 c +85 c +25 c - 40 c v = 1.8 v i = 10 ma out out 1.901.88 1.86 1.84 1.82 1.80 1.78 1.76 1.74 1.72 1.70 v out (v) 2.3 2.7 3.1 3.5 3.9 4.3 4.7 v (v) in 5.5 5.1 +125 c +85 c +25 c - 40 c v = 1.8 v i = 300 ma out out 0 100 150 300 i (ma) out 1.901.88 1.86 1.84 1.82 1.80 1.78 1.76 1.74 1.72 1.70 v (v) out 50 200 +125 c +85 c +25 c - 40 c v = 1.8 v out 250 350300 250 200 150 100 50 0 v (mv) do 2.25 2.75 3.25 3.75 4.25 4.75 v (v) in +125 c +85 c +25 c C40 c i = 300 ma out 1.901.88 1.86 1.84 1.82 1.80 1.78 1.76 1.74 1.72 1.70 v (v) out - 40 - 25 - 10 5 20 35 50 65 80 95 110 temperature ( c) 125 10ma150ma 200ma v = 1.8 v out 0 100 150 300 i (ma) out 300250 200 150 100 50 0 v (mv) do 50 200 +125 c +85 c +25 c - 40 c v = 4.8 v out 250
7 tlv702-q1 www.ti.com slvsc35c ? august 2013 ? revised january 2018 product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated typical characteristics (continued) over operating temperature range (t j = ? 40 c to +125 c), v in = v out(nom) + 0.5 v or 2 v, whichever is greater; i out = 10 ma, v en = v in , c out = 1 f, unless otherwise noted. typical values are at t j = 25 c. figure 7. ground pin current vs input voltage figure 8. ground pin current vs load figure 9. ground pin current vs temperature figure 10. shutdown current vs input voltage figure 11. current limit vs input voltage figure 12. power-supply ripple rejection vs frequency 100 9080 70 60 50 40 30 20 10 0 psrr (db) 10 100 1 k 10 k 100 k 1 m 10 m frequency (hz) i = 150 ma out i = 10 ma out v v = 0.5 v in out - 700600 500 400 300 200 100 0 i lim (ma) 2.3 2.7 3.1 3.5 3.9 4.3 4.7 v (v) in 5.5 5.1 v = 1.8 v out +125 c +85 c +25 c - 40 c 450400 350 300 250 200 150 100 50 0 i gnd ( m a) 0 i (ma) out 300 +125 c +85 c +25 c - 40 c v = 1.8 v out 50 150 250 100 200 5045 40 35 30 25 20 15 10 50 i gnd ( a m ) 2.1 2.6 3.1 3.6 4.1 4.6 5.1 v (v) in 5.6 +125 c +85 c +25 c - 40 c v = 1.8 v out 2.5 2 1.5 1 0.5 0 i shdn ( a m ) 2.1 2.6 3.1 3.6 4.1 4.6 5.1 v (v) in 5.6 +125 c +85 c +25 c - 40 c v = 1.8 v out 5045 40 35 30 25 20 15 10 50 i ( a) m gnd - 40 - 25 - 10 5 20 35 50 65 80 95 110 temperature ( c) 125 v = 1.8 v out
8 tlv702-q1 slvsc35c ? august 2013 ? revised january 2018 www.ti.com product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated typical characteristics (continued) over operating temperature range (t j = ? 40 c to +125 c), v in = v out(nom) + 0.5 v or 2 v, whichever is greater; i out = 10 ma, v en = v in , c out = 1 f, unless otherwise noted. typical values are at t j = 25 c. figure 13. power-supply ripple rejection vs input voltage figure 14. output spectral noise density vs frequency figure 15. load transient response figure 16. load transient response figure 17. load transient response figure 18. load transient response 100 ma/div 50 mv/div 10 s/div m v out i out 200 ma 0 ma t = t = 1 s r f m v out = 1.8 v 50 ma/div 20 mv/div 10 s/div m v out i out 50 ma 0 ma t = t = 1 s r f m v out = 1.8 v 200 ma/div 100 mv/div 10 s/div m v out 300 ma 0 ma t = t = s r f m 1 i out v out = 1.8 v 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 input voltage (v) 8070 60 50 40 30 20 10 0 psrr (db) 10 khz 100 khz 1 khz v = 1.8 v out 20 ma/div 5 mv/div 10 s/div m v out v out = 1.8 v i out 10 ma 0 ma t = t = 1 s r f m 10 1 0.1 0.01 0.001 output spectral noise density ( v/ ) m ? hz 10 100 1 k 10 k 100 k 1 m 10 m frequency (hz) v = 1.8 v out i = 10 ma c = c = 1 f out in out m
9 tlv702-q1 www.ti.com slvsc35c ? august 2013 ? revised january 2018 product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated typical characteristics (continued) over operating temperature range (t j = ? 40 c to +125 c), v in = v out(nom) + 0.5 v or 2 v, whichever is greater; i out = 10 ma, v en = v in , c out = 1 f, unless otherwise noted. typical values are at t j = 25 c. figure 19. line transient response figure 20. line transient response figure 21. line transient response figure 22. v in ramp up, ramp down response 1 v/div 10 mv/div 1 ms/div slew rate = 1 v/ s m v = 1.8 v i = 300 ma out out 5.5 v v in 2.1 v v out 1 v/div 200 ms/div v out v in v = 1.8 v out i 1 ma out = 1 v/div 5 mv/div 1 ms/div v out slew rate = 1 v/ s m v in 2.9 v 2.3 v v = 1.8 v i 300 ma out out = 1 v/div 5 mv/div 1 ms/div v out v in 2.9 v 2.3 v v = 1.8 v i 1 ma out out = slew rate = 1 v/ s m
10 tlv702-q1 slvsc35c ? august 2013 ? revised january 2018 www.ti.com product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the tlv702-q1 series of low-dropout (ldo) linear regulators are low quiescent current devices with excellent line and load transient performance. these ldos are designed for power-sensitive applications. a precision bandgap and error amplifier provides overall 2% accuracy. low output noise, very high power-supply rejection ratio (psrr), and low dropout voltage make this series of devices ideal for most battery-operated handheld equipment. all device versions have integrated thermal shutdown, current limit, and undervoltage lockout (uvlo) protections. 7.2 functional block diagrams figure 23. tlv702-q1 block diagram 7.3 feature description 7.3.1 internal current limit the tlv702-q1 internal current limit protection helps to protect the regulator during fault conditions. during current limit operation, the output sources a fixed amount of current that is largely independent of the output voltage. in such a case, the output voltage is not regulated, and is v out = i cl r load . the pmos pass transistor dissipates (v in ? v out ) i cl until thermal shutdown is triggered and the device turns off. as the device cools, the device is turned on by the internal thermal shutdown circuit. if the fault condition continues, the device cycles between current limit operation and thermal shutdown. see thermal consideration for more details. the pmos pass element in the tlv702-q1 has a built-in body diode that conducts current when the voltage at the out pin exceeds the voltage at in. this current is not limited; if extended reverse-voltage operation is anticipated, externally limit the output current to 5% of the rated i out specification. thermal shutdown current limit uvlo bandgap in en out logic gnd tlv702-q1 series
11 tlv702-q1 www.ti.com slvsc35c ? august 2013 ? revised january 2018 product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated feature description (continued) 7.3.2 shutdown the enable pin (en) is active high. the device is enabled when voltage at en pin exceeds 0.9 v. the device is turned off when the en pin is held at less than 0.4 v. when shutdown capability is not required, connect the en pin to the in pin. 7.3.3 dropout voltage the tlv702-q1 uses a pmos pass transistor to achieve low dropout. when (v in ? v out ) is less than the dropout voltage (v do ), the pmos pass device is in the linear (triode) region of operation. the input-to-output resistance is equal to the drain-source on-state resistance (r ds(on) ) of the pmos pass element. v do scales approximately with output current because the pmos device behaves as a resistor in dropout. as with any linear regulator, psrr and transient response are degraded as (v in ? v out ) approaches dropout. this effect is shown in figure 13 . 7.3.4 undervoltage lockout the tlv702-q1 uses a uvlo circuit to keep the output shut off until internal circuitry is operating properly. 7.4 device functional modes 7.4.1 normal operation the device regulates to the nominal output voltage under the following conditions: ? the input voltage is greater than the nominal output voltage added to the dropout voltage. ? the output current is less than the current limit. ? the input voltage is greater than the uvlo voltage. 7.4.2 dropout operation if the input voltage is less than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. in this condition, the output voltage is the same as the input voltage minus the dropout voltage. the transient performance of the device is significantly degraded because the pass device is in a triode state and no longer regulates the output voltage of the ldo. line or load transients in dropout may result in large output voltage deviations. table 1 lists the conditions that lead to the different modes of operation. table 1. device functional mode comparison operating mode parameter v in i out normal mode v in > v out(nom) + v do i out < i cl dropout mode v in < v out(nom) + v do i out < i cl current limit v in > uvlo i out > i cl
12 tlv702-q1 slvsc35c ? august 2013 ? revised january 2018 www.ti.com product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tlv702-q1 belongs to a new family of next-generation value ldo regulators. these devices consume low quiescent current and deliver excellent line and load transient performance. these characteristics, combined with low noise and very good psrr with little (v in ? v out ) headroom, make this family of devices ideal for portable rf applications. this family of regulators offers current limit and thermal protection, and is specified from ? 40 c to +125 c. 8.2 typical application figure 24. typical application circuit 8.2.1 design requirements table 2 lists the design parameters. table 2. design parameters parameter design requirement input voltage 2.5 v to 3.3 v output voltage 1.8 v output current 100 ma tlv702-q1 gnd en in out v in v out on off c in 1 f ceramic c out
13 tlv702-q1 www.ti.com slvsc35c ? august 2013 ? revised january 2018 product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated 8.2.2 detailed design procedure 8.2.2.1 input and output capacitor requirements 1- f x5r- and x7r-type ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent series resistance (esr) over temperature. however, the tlv702-q1 is designed to be stable with an effective capacitance of 0.1 f or larger at the output. thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance under operating bias voltage and temperature is greater than 0.1 f. this effective capacitance refers to the capacitance that the ldo sees under operating bias voltage and temperature conditions; that is, the capacitance after taking both bias voltage and temperature derating into consideration. in addition to allowing the use of lower-cost dielectrics, this capability of being stable with 0.1- f effective capacitance also enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained applications. using a 0.1- f rated capacitor at the output of the ldo does not ensure stability because the effective capacitance under the specified operating conditions must not be less than 0.1 f. maximum esr should be less than 200 m . although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1- f to 1- f, low esr capacitor across the in pin and gnd pin of the regulator. this capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. a higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. if source impedance is more than 2 , a 0.1- f input capacitor may be necessary for stability. 8.2.2.2 transient response as with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude, but increases the duration of the transient response. 8.2.3 application curves figure 25. load transient response figure 26. line transient response 1 v/div 5 mv/div 1 ms/div v out v in 2.9 v 2.3 v v = 1.8 v i 1 ma out out = slew rate = 1 v/ s m 50 ma/div 20 mv/div 10 s/div m v out i out 50 ma 0 ma t = t = 1 s r f m v out = 1.8 v
14 tlv702-q1 slvsc35c ? august 2013 ? revised january 2018 www.ti.com product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated 9 power supply recommendations connect a low output impedance power supply directly to the in pin of the tlv702-q1. inductive impedances between the input supply and the in pin can create significant voltage excursions at the in pin during start-up or load transient events. 9.1 power dissipation the ability to remove heat from the die is different for each package type, presenting different considerations in the printed-circuit-board (pcb) layout. the pcb area around the device that is free of other components moves the heat from the device to the ambient air. refer to thermal information for thermal performance on the tlv702-q1 evaluation module (evm). the evm is a two-layer board with two ounces of copper per side. power dissipation depends on input voltage and load conditions. power dissipation (p d ) is equal to the product of the output current and the voltage drop across the output pass element, as shown in equation 1 . (1) 10 layout 10.1 layout guidelines place the input and output capacitors as close to the device pins as possible. to improve ac performance such as psrr, output noise, and transient response, design the board with separate ground planes for v in and v out , with the ground plane connected only at the gnd pin of the device. in addition, connect the ground connection for the output capacitor directly to the gnd pin of the device. high-esr capacitors may degrade psrr performance. 10.1.1 thermal consideration thermal protection disables the output when the junction temperature rises to approximately 165 c, allowing the device to cool. when the junction temperature cools to approximately 145 c, the output circuitry is again enabled. depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. this cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. for reliable operation, limit junction temperature to 125 c maximum. to estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. the internal protection circuitry of the tlv702-q1 is designed to protect against overload conditions but is not intended to replace proper heatsinking. continuously running the tlv702-q1 into thermal shutdown degrades device reliability. p = (v v ) i - d in out out
15 tlv702-q1 www.ti.com slvsc35c ? august 2013 ? revised january 2018 product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated layout guidelines (continued) 10.1.2 package mounting solder pad footprint recommendations for the tlv702-q1 are available from the ti website at www.ti.com . the recommended layout examples for the ddc and dse packages are shown in figure 27 and figure 28 , respectively. 10.2 layout examples figure 27. layout example for the ddc and dbv packages figure 28. layout example for the dse package c out v out v in gnd plane c in represents via used for application specific connections in gnd en nc out c out v out v in gnd plane c in represents via used for application specific connections in gnd out nc en nc
16 tlv702-q1 slvsc35c ? august 2013 ? revised january 2018 www.ti.com product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated (1) for the most current package and ordering information see the package option addendum at the end of this document, or visit the device product folder at www.ti.com . (2) output voltages from 1.2 v to 4.8 v in 50-mv increments are available. contact factory for details and availability. 11 device and documentation support 11.1 device support 11.1.1 development support 11.1.1.1 spice models computer simulation of circuit performance using spice is often useful when analyzing the performance of analog circuits and systems. a spice model for the tlv702 is available through the product folders under tools & software . 11.1.2 device nomenclature table 3. ordering information (1) product v out (2) tlv702 xx yyyz xx is nominal output voltage (for example, 28 = 2.8 v). yyy is the package designator. z is tape and reel quantity (r = 3000, t = 250). 11.2 documentation support 11.2.1 related documentation for related documentation see the following: using the tlv700xxevm-503 evaluation module 11.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.5 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
17 tlv702-q1 www.ti.com slvsc35c ? august 2013 ? revised january 2018 product folder links: tlv702-q1 submit documentation feedback copyright ? 2013 ? 2018, texas instruments incorporated 11.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 27-jan-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tlv702125qdbvrq1 preview sot-23 dbv 5 3000 tbd call ti call ti -40 to 125 tlv70212qdbvrq1 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 1b5h tlv70212qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 h9 tlv70213qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 h8 tlv70215qdbvrq1 preview sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1b6h tlv70215qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 hb tlv70218qdbvrq1 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 1b7h tlv70218qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 hc tlv70225qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 g7 tlv70227qdbvrq1 preview sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1b8h tlv70227qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 h7 tlv70228qdbvrq1 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 1b9h tlv70228qddcrq1 active sot-23-thin ddc 5 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 sjv tlv70228qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 hd tlv70229qdbvrq1 preview sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1bah tlv70229qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 h1 TLV70230QDBVRQ1 preview sot-23 dbv 5 3000 tbd call ti call ti -40 to 125 tlv70230qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 he
package option addendum www.ti.com 27-jan-2018 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tlv70231qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 hf tlv70232qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 hg tlv70233qdbvrq1 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 1bbh tlv70233qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 h2 tlv70236qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 h3 tlv70245qdserq1 active wson dse 6 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 hh (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 27-jan-2018 addendum-page 3 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of tlv702-q1 : ? catalog: tlv702 note: qualified version definitions: ? catalog - ti's standard catalog product
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tlv70212qdbvrq1 sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 tlv70212qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70213qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70215qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70218qdbvrq1 sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 tlv70218qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70225qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70227qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70228qdbvrq1 sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 tlv70228qddcrq1 sot- 23-thin ddc 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv70228qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70229qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70230qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70231qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70232qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70233qdbvrq1 sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 tlv70233qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 package materials information www.ti.com 24-jan-2018 pack materials-page 1
device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tlv70236qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 tlv70245qdserq1 wson dse 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 q2 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tlv70212qdbvrq1 sot-23 dbv 5 3000 183.0 183.0 20.0 tlv70212qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70213qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70215qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70218qdbvrq1 sot-23 dbv 5 3000 183.0 183.0 20.0 tlv70218qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70225qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70227qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70228qdbvrq1 sot-23 dbv 5 3000 183.0 183.0 20.0 tlv70228qddcrq1 sot-23-thin ddc 5 3000 195.0 200.0 45.0 tlv70228qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70229qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70230qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70231qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70232qdserq1 wson dse 6 3000 203.0 203.0 35.0 package materials information www.ti.com 24-jan-2018 pack materials-page 2
device package type package drawing pins spq length (mm) width (mm) height (mm) tlv70233qdbvrq1 sot-23 dbv 5 3000 183.0 183.0 20.0 tlv70233qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70236qdserq1 wson dse 6 3000 203.0 203.0 35.0 tlv70245qdserq1 wson dse 6 3000 203.0 203.0 35.0 package materials information www.ti.com 24-jan-2018 pack materials-page 3

www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2

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